The present invention relates to a semiconductor layered structure and a semiconductor device using the layered structure, and particularly to a layered structure composed of different semiconductor layers capable of reducing defects and a semiconductor device using the layered structure.
In recent years, layered structures composed of different semiconductor layers are extensively used for realizing various semiconductor devices or improving the performances thereof.
Of these semiconductor layered structures, a type with a large lattice mismatch has a disadvantage in generating defects, which are called dislocations, in a single crystal growth layer formed on a single crystal substrate. Such dislocations are generated during the growth of a single crystal growth layer, and some cases, they are generated to relax strains caused by a difference in thermal expansion coefficient in a process of cooling the substrate after the growth. The generation of dislocations causes the scattering of carriers, reduction of the activation ratio of n-type and p-type impurities, and lowering of the life due to re-combination of minority carriers, thus deteriorating the characteristics of semiconductor devices.
Some attempts have been made to reduce the above dislocations in a single crystal growth layer. For example, in Oyobuturi Vol. 61, No. 2, P. 126 (in Japanese), GaAs is grown on Si by a two-step growth method, wherein a vicinal substrate is used and a strained layer super lattice is inserted.
Another method has been disclosed in Extended Abstracts (The 53rd Autumn Meeting, 1992); The Japan Society of Applied Physics (p. 303), wherein an intermediate layer of InAs is inserted at the interface of a layered structure composed of an Si layer and a GaAs layer, to confine dislocations in the InAs layer, thus reducing the dislocations in the GaAs layer equivalent to the above-described single crystal growth layer. In this method, only the InAs layer having a low melting point is melted by heating the layered structure, to generate dislocations in the InAs layer, thus relaxing a strain energy stored in the GaAs layer.